The present invention relates to a method for arbitrating a memory bus, access to which is requested by a plurality of data transfer circuits, and a memory control circuit for controlling a memory bus and a memory connected to the memory bus using the above method. In particular, the present invention relates to a method for arbitrating a memory bus connected to a plurality of data transfer circuits suitable for real-time processing such as moving picture processing, and a memory control circuit for performing the above method.
Some video apparatuses incorporates a memory device such as an SDRAM (Synchronous DRAM) that uses a DRAM (Dynamic Random Access Memory) as a core in order to store video data for video signal processing. This type of memory device is usually arranged so that both the data writing operation and the data reading operation are carried out using the same memory bus. The memory device, in which a write request and a read request are produced at the same time, should be equipped with an arbitrating device for arbitrating the memory bus in order to enable data transfer on a selective and time-shared basis in response to these requests. Further, even when a dual port memory is used which enables simultaneous execution of the writing operation and the reading operation, if more than two data transfer circuits request the access to the memory bus at the same time, it is required that the memory device be equipped with an arbitrating device for arbitrating the memory bus.
One of methods for arbitrating a memory bus when a plurality of data transfer circuits request the access to the memory bus is disclosed in, for example, a Japanese Patent No. 3,033,747 publication. A memory control circuit arranged with use of this prior art technique is shown in FIG. 12.
In FIG. 12, a reference numeral 63 denotes a graphics data generation circuit for generating graphics data to be displayed on a display unit, a reference numeral 64 denotes a first SDRAM for storing the data generated by the graphics data generation circuit 63, a reference numeral 65 denotes a second SDRAM for storing the data generated by the graphics data generation circuit 63, a reference numeral 66 denotes a first display controller for transferring data stored in the first SDRAM 64 to a first display unit 71 (to be explained later), and a reference numeral 67 denotes a second display controller for transferring data stored in the second SDRAM 65 to a second display unit 72 (to be explained later). Further, in FIG. 12, a reference numeral 68 denotes a first memory bus which is used for transmitting and receiving data, addresses, commands and so on by the graphics data generation circuit 63, the first SDRAM 64 and the first display controller 66. Furthermore, in FIG. 12, a reference numeral 69 denotes a second memory bus which is used for transmitting and receiving data, addresses, commands and so on by the graphics data generation circuit 63, the second SDRAM 65 and the second display controller 67. Moreover, in FIG. 12, a reference numeral 70 denotes a bus arbiter which controls timing of data transfer executed by the graphics data generation circuit 63, the first display controller 66 and the second display controller 67 in order to arbitrate the first memory bus 68 and the second memory bus 69. Additionally, in FIG. 12, a reference numeral 71 denotes the first display unit which displays data transferred from the first display controller 66, and a reference numeral 72 denotes the second display unit which displays data transferred from the second display controller 67.
The prior art memory control circuit having the above-mentioned arrangements as shown in FIG. 12 operates as follows.
The graphics data generation circuit 63 generates graphics data to be displayed on the first display unit 71 and the second display unit 72. When completing generation of the graphics data to be displayed on the first display unit 71, the graphics data generation circuit 63 transmits a first write request signal to the bus arbiter 70 to write the graphics data into the first SDRAM 64. Further, the first display controller 66 incorporates a synchronization signal generation circuit for generating vertical and horizontal synchronization signals to drive the first display unit 71. The first display controller 66, whenever detecting a reference edge in the horizontal synchronization signal generated therein within an effective display period, transmits a first read request signal to the bus arbiter 70 to read out data stored in the first SDRAM 64 and to transfer it to the first display unit 71.
Similarly, when completing generation of graphics data to be displayed on the second display unit 72, the graphics data generation circuit 63 transmits a second write request signal to the bus arbiter 70 to write the graphics data into the second SDRAM 65. The second display controller 67 incorporates a synchronization signal generation circuit for generating vertical and horizontal synchronization signals to drive the second display unit 72. The second display controller 67, whenever detecting a reference edge in the horizontal synchronization signal generated therein within an effective display period, transmits a second read request signal to the bus arbiter 70 to read out data stored in the second SDRAM 65 and to transfer it to the second display unit 72. Generally, the period of the synchronization signal generated by the first display controller 66 is different from the period of the synchronization signal generated by the second display controller 67.
The bus arbiter 70 receives first and second write request signals generated by the graphics data generation circuit 63, a first read request signal generated by the first display controller 66, and a second read request signal generated by the second display controller 67. In response to four types of request signals received, the bus arbiter 70 generates four types of acknowledge signals for enabling execution of data transfer. More specifically, when data transfer is not executed in the first memory bus 68 during transmission of the first write request signal, the bus arbiter 70 transmits a first write acknowledge signal to the graphics data generation circuit 63. When data transfer is not executed in the first memory bus 68 during transmission of the second write request signal, the bus arbiter 70 transmits a second write acknowledge signal to the first display controller 66. When data transfer is not executed in the second memory bus 69 during transmission of the first read request signal, the bus arbiter 70 transmits a first acknowledge signal to the graphics data generation circuit 63. When data transfer is not executed in the second memory bus 69 during transmission of the second read request signal, the bus arbiter 70 transmits a second read acknowledge signal to the second display controller 67.
When receiving the first write acknowledge signal, the graphics data generation circuit 63 transfers data generated therein to the first SDRAM 64 via the first memory bus 68. When completing the data transfer, the graphics data generation circuit 63 stops transmission of the first write request signal to the bus arbiter 70. Further, when receiving the first read acknowledge signal, the first display controller 66 transfers data to be displayed for one horizontal period from the first SDRAM 64 to the first display controller 66 via the first memory bus 68. When completing the data transfer, the first display controller 66 stops transmission of the first read request signal to the bus arbiter 70. Further, the data transferred from the first SDRAM 64 to the first display controller 66 is transferred to the first display unit 71 together with the horizontal and vertical synchronization signals generated by the first display controller 66.
Similarly, when receiving the second write acknowledge signal, the graphics data generation circuit 63 transfers the generated data to the second SDRAM 65 via the second memory bus 69. When completing the data transfer, the graphics data generation circuit 63 stops transmission of the second write request signal to the bus arbiter 70. Meanwhile, when receiving the second read acknowledge signal, the second display controller 67 transfers data to be displayed for one horizontal period from the second SDRAM 65 to the second display controller 67 via the second memory bus 69. When completing the data transfer, the second display controller 67 stops transmission of the second read request signal to the bus arbiter 70. Further, the data transferred from the second SDRAM 65 to the second display controller 67 is transferred to the second display unit 72 together with the horizontal and vertical synchronization signals generated by the second display controller 67.
In the data transfer, the graphics data generation circuit 63, the first display controller 66 and the second display controller 67 generate addresses and commands necessary for the data transfer, and transmit the generated addresses and commands to the first or second SDRAM 64 or 65 via the first or second memory bus 68 or 69 respectively.
FIG. 13 is a timing chart for explaining how the bus arbiter 70 arbitrates the first memory bus 68 using the request signal and the acknowledge signal. In FIG. 13, the horizontal synchronization signal generated by the first display controller 66 has a negative polarity, and both of the request and acknowledge signals are high active signals.
As shown in FIG. 13, when detecting a falling edge as a reference edge in the horizontal synchronization signal at a timing ta, the first display controller 66 turns the first read request signal to its high level to ask the bus arbiter 70 to execute the data transfer from the first display controller 66 to the first SDRAM 64. At this time, if the graphics data generation circuit 63 is executing the data transfer via the first memory bus 68 at the timing ta, then the bus arbiter 70 keeps the level of the first read acknowledge signal low to prevent the first display controller 66 from executing the data transfer.
Next, when completing the data transfer at a timing tb, the graphics data generation circuit 63 turns the first write request signal to its low level, as shown in FIG. 13. In response to this, the bus arbiter 70 turns the first write acknowledge signal to its low level and turns the first read acknowledge signal to its high level, thus causing the first display controller 66 to start the data transfer.
As shown in FIG. 13, when the graphics data generation circuit 63 again generates the first write request signal at a timing tc, if the first display controller 66 is executing the data transfer, then the bus arbiter 70 keeps the level of the first write acknowledge signal low until a timing td at which the first display controller 66 completes the data transfer, thereby preventing the graphics data generation circuit 63 from executing the data transfer.
In this case, the amount of data generated by the graphics data generation circuit 63 is not always constant. Thus, in the case where the amount of data to be transferred is small, when the graphics data generation circuit 63 has stopped the data transfer, the first read request signal still sometimes remains at its low level. This phenomenon corresponds to a situation at a timing te shown in FIG. 13. At this time, the first memory bus 68 is in its idle state where no data transfer is executed, until any one of the first write request signal and the read request signal becomes high level (e.g., a duration from a timing te to a timing tf shown in FIG. 13). Accordingly, when the level of the first read request signal is changed to high at the timing tf, the bus arbiter 70 immediately turns the first read acknowledge signal to high level to cause the first display controller 66 to start the data transfer. In particular, if there is a possibility that both levels of the first write and read request signals are changed to high during the idle state of the first memory bus 68, it should be previously determined which request signals the bus arbiter 70 should preferentially respond to.
How to arbitrate the second memory bus 69 using the second write and read request signals as well as the second write and read acknowledge signals is also exactly the same as how to arbitrate the first memory bus 68. In this manner, two types of data transfer per one memory bus with the memory used as transfer destination and transfer source can be arbitrated.
In the aforementioned prior art memory control circuit, the memory bus arbitration is carried out on the assumption that always two data transfer circuits are connected to a single memory bus. Accordingly, the prior art memory control circuit has a problem that the number of memory devices is required to be the same as the number of display units as the final data transfer destinations and, therefore, when the number of display units is especially large, a large number of memory devices must be used. Generally, as the number of parts in an electric circuit increases, substrate area, cost, and so on are also undesirably increased.
It is an object of the present invention to provide a method for arbitrating a memory bus and a memory control circuit which can arbitrate a memory bus without failure even when a plurality of data transfer circuits request access to the memory bus at any given timing.
According to an aspect of the present invention, a memory control circuit for controlling a memory bus and a memory connected to the memory bus includes a plurality of buffers which temporarily store at least either of data to be transferred to the memory or data transferred from the memory; a plurality of counters having count values respectively, the count values corresponding to numbers of pieces of data stored in the plurality of buffers respectively; a plurality of data transfer circuits which perform data transfer between the memory and the plurality of buffers using the memory bus; and a bus arbiter including a state machine which has a plurality of states associated with the plurality of data transfer circuits respectively and sets one of the plurality of states as a current state, transition of the current state of the state machine taking place in accordance with a predetermined transition condition. (1) Each of the plurality of data transfer circuits transmits a request signal demanding start of the data transfer to the bus arbiter on the basis of at least one of the count values of the plurality of counters. (2) The data transfer circuit associated with the current state of the state machine transmits the request signal to the bus arbiter, the bus arbiter transmits an acknowledge signal granting start of the data transfer to the data transfer circuit associated with the current state of the state machine. (3) Each of the plurality of data transfer circuits starts the data transfer at receipt of the acknowledge signal from the bus arbiter in response to the request signal, and stops the data transfer being executed on the basis of either number of pieces of data transferred after the receipt of the acknowledge signal or the count value of at least one of the plurality of counters. (4) When the data transfer circuit associated with the current state of the state machine either does not transmit the request signal or has stopped the data transfer being executed, the bus arbiter does not transmit the acknowledge signal to the data transfer circuit associated with the current state of the state machine, and transition of the current state of the state machine to a renewed current state takes place in accordance with the predetermined transition condition. (5) The operations (1) to (4) are repeated. The above-mentioned memory control circuit can arbitrate a memory bus without failure even when a plurality of data transfer circuits request access to the memory bus at any given timing, thereby making it possible to transfer data without failure between the memory control circuit and an external circuit.
In the operation (2), the following operation may be performed. Even when the data transfer circuit associated with the current state of the state machine is transmitting the request signal, if specific at least one of the plurality of data transfer circuits associated with a state other than the current state of the state machine is transmitting the request signal, the bus arbiter does not transmit the acknowledge signal to the data transfer circuit associated with the current state of the state machine, and transition of the current state of the state machine to a renewed current state takes place in accordance with the predetermined transition condition. The above-mentioned memory control circuit can afford more opportunities to the data transfer circuit having higher priority.
Further, the memory control circuit may be constructed as follows. When the state machine has a plurality of states next to the current state, the state machine sets one of the plurality of states next to the current state as a renewed current state on the basis of the request signal transmitted by specific at least one of the plurality of data transfer circuits.
According to another aspect of the present invention, a memory control circuit for controlling a memory bus and a memory connected to the memory bus includes a plurality of buffers which temporarily store at least either of data to be transferred to the memory or data transferred from the memory; a plurality of counters having count values respectively, the count values corresponding to numbers of pieces of data stored in the plurality of buffers respectively; a plurality of data transfer circuits which perform data transfer between the memory and the plurality of buffers using the memory bus; and a bus arbiter including an instruction queue formed by a shift register. (1) Each of the plurality of data transfer circuits transmits a request signal demanding start of the data transfer to the bus arbiter on the basis of at least one of the count values of the plurality of counters. (2) If the bus arbiter has received the request signal from at least one of the plurality of data transfer circuits, the bus arbiter enters a data transfer instruction, which is associated with at least one of the plurality of data transfer circuits that has transmitted the request signal, into a tail of the instruction queue. (3) The bus arbiter transmits an acknowledge signal granting start of the data transfer to the data transfer circuit associated with a data transfer instruction held at ahead of the instruction queue. (4) Each of the plurality of data transfer circuits starts the data transfer at receipt of the acknowledge signal from the bus arbiter in response to the request signal, and stops the data transfer being executed on the basis of either number of pieces of data transferred after the receipt of the acknowledge signal or the count value of at least one of the plurality of counters. (5) When the data transfer circuit has stopped the data transfer, the bus arbiter deletes the data transfer instruction associated with the data transfer circuit that has stopped the data transfer from the instruction queue and the bus arbiter shifts contents of the instruction queue in a latter stage by one stage toward the head of the instruction queue. (6) The operations (1) to (5) are repeated.
In the operation (1), the following operation may be performed. Even when any of the plurality of data transfer circuits is transmitting the request signal, if specific at least one of the plurality of data transfer circuits other than the data transfer circuit that is transmitting the request signal, is transmitting the request signals or if the data transfer instruction associated with specific at least one of the plurality of data transfer circuits other than the data transfer circuit that is transmitting the request signal, is held in the instruction queue, the operation (2) is not executed so that the bus arbiter does not enter the data transfer instruction, which is associated with the data transfer circuit that is transmitting the request signal, into a tail of the instruction queue.
Further, the memory control circuit may be constructed as follows. Even when the data transfer instruction is held at the head of the instruction queue, if specific at least one of the plurality of data transfer circuits, which is other than the data transfer circuit associated with the data transfer instruction held at the head of the instruction queue, is transmitting the request signal or if the data transfer instruction associated with specific at least one of the plurality of data transfer circuits, which is other than the data transfer circuit associated with the data transfer instruction held at the head of the instruction queue, is held in the instruction queue, the operation (3) is not executed so that the bus arbiter does not transmit the acknowledge signal to the data transfer circuit associated with the data transfer instruction held at the head of the instruction queue.
According to further aspect of the present invention, a memory control circuit for controlling a memory bus and a memory connected to the memory bus includes a plurality of buffers which temporarily store at least either of data to be transferred to the memory or data transferred from the memory; a plurality of counters having count values respectively, the count values corresponding to numbers of pieces of data stored in the plurality of buffers respectively; a plurality of data transfer circuits which perform data transfer between the memory and the plurality of buffers using the memory bus; and a bus arbiter including an instruction queue formed by a shift register and a state machine which has a plurality of states each of which is associated with one of the plurality of data transfer circuits or the instruction queue. The state machine sets one of the plurality of states as a current state, and transition of the current state of the state machine takes place in accordance with a predetermined transition condition. At least one of the plurality of states of the state machine is associated with the instruction queue. Some of the plurality of data transfer circuits are associated with the plurality of states of the state machine respectively, and a remainder of the plurality of data transfer circuits is associated with the instruction queue. (1) Each of the plurality of data transfer circuits transmits a request signal demanding start of the data transfer to the bus arbiter on the basis of at least one of the count values of the plurality of counters. (2) When the data transfer circuit associated with the current state of the state machine transmits the request signal to the bus arbiter, the bus arbiter transmits an acknowledge signal granting start of the data transfer to the data transfer circuit associated with the current state of the state machine. (3) Each of the plurality of data transfer circuits starts the data transfer at receipt of the acknowledge signal from the bus arbiter in response to the request signal, and stops the data transfer being executed on the basis of either number of pieces of data transferred after the receipt of the acknowledge signal or the count value of at least one of the plurality of counters. (4) When the data transfer circuit associated with the current state of the state machine either does not transmit the request signal or has stopped the data transfer being executed, the bus arbiter does not transmit the acknowledge signal to the data transfer circuit associated with the current state of the state machine, and transition of the current state of the state machine to a renewed current state takes place in accordance with the predetermined transition condition. (5) Only when the current state of the state machine is associated with the instruction queue, at least a part of the data transfer instructions held in the instruction queue is executed sequentially from the head of the instruction queue, and after that transition of the current state of the state machine to a renewed current state takes place in accordance with the predetermined transition condition. (6) The operations (1) to (5) are repeated.
In the operation (5), the following operations may be performed. (5-1) If the bus arbiter receives the request signal from any of the plurality of data transfer circuits associated with the instruction queue, the bus arbiter enters the data transfer instruction associated with the data transfer circuit which has transmitted the request signal into the tail of the instruction queue. (5-2) The bus arbiter transmits the acknowledge signal granting start of the data transfer to the data transfer circuit associated with the data transfer instruction held at the head of the instruction queue. (5-3) Each of the data transfer circuits associated with the instruction queue starts the data transfer at receipt of the acknowledge signal from the bus arbiter in response to the request signal, and stops the data transfer being executed on the basis of either number of pieces of data transferred after the receipt of the acknowledge signal or the count values of at least one of the plurality of counters. (5-4) When the data transfer circuit has stopped the data transfer, the bus arbiter deletes the data transfer instruction associated with the data transfer circuit that has stopped the data transfer from the instruction queue and the bus arbiter shifts contents of the instruction queue in a latter stage by one stage toward the head of the instruction queue. (5-5) The operations (5-1) to (5-4) are repeated at least once.
In the operation (5-1), the following operations may be performed. Even when any of the plurality of data transfer circuits is transmitting the request signal, if specific at least one of the plurality of data transfer circuits other than the data transfer circuit that is transmitting the request signal, is transmitting the request signals or if the data transfer instruction associated with specific at least one of the plurality of data transfer circuits other than the data transfer circuit that is transmitting the request signal, is held in the instruction queue, the operation (5-2) is not executed so that the bus arbiter does not enter the data transfer instruction, which is associated with the data transfer circuit that is transmitting the request signal, into a tail of the instruction queue.
Further, the memory control circuit may be constructed as follows. Even when the data transfer instruction is held at the head of the instruction queue, if specific at least one of the plurality of data transfer circuits, which is other than the data transfer circuit associated with the data transfer instruction held at the head of the instruction queue, is transmitting the request signal or if the data transfer instruction associated with specific at least one of the plurality of data transfer circuits, which is other than the data transfer circuit associated with the data transfer instruction held at the head of the instruction queue, is held in the instruction queue, the operation (5-3) is not executed so that the bus arbiter does not transmit the acknowledge signal to the data transfer circuit associated with the data transfer instruction held at the head of the instruction queue.
Further, the memory control circuit may be constructed as follows. Even when the data transfer instruction is held in the instruction queue associated with the current state of the state machine, if specific at least one of data transfer circuits associated with states of the state machine other than the current state is transmitting their request signal, transition of the current state of the state machine takes place in accordance with the predetermined transition condition, and the bus arbiter does not transmit the acknowledge signal to the data transfer circuit associated with the data transfer instruction held at the head of the instruction queue.
Furthermore, the memory control circuit may be constructed as follows. Even while the data transfer circuit is executing data transfer, if specific at least one of the data transfer circuits other than the data transfer circuit which is executing the data transfer starts transmission of the request signals, the bus arbiter issues an instruction to the data transfer circuit which is executing the data transfer to stop the data transfer being executed.
Also, the memory control circuit may be constructed as follows. Each of the plurality of counters generates the count value on the basis of a read instruction to each of the plurality of buffers, a write instruction to the plurality of buffers, a read instruction to the memory, and a write instruction to the memory.
Moreover, the memory control circuit may be constructed as follows. Each of the plurality of counters includes an inverted-pulse generation circuit for generating a pulse inverted each time the read or write instruction to the plurality of buffers is issued and a differentiation circuit for detecting an edge in the pulse generated by the inverted-pulse generation circuit, and each of the plurality of counters generates the count value on the basis of a detection result of the differentiation circuit, the read instruction to the memory, and the write instruction to the memory.
Further, the memory control circuit may be constructed as follows. Each of the plurality of data transfer circuits generates the request signal, when the count value of each of the plurality of data transfer circuits becomes above or below a predetermined set value.
Furthermore, the memory control circuit may be constructed as follows. Each of the plurality of data transfer circuits stops the data transfer, when the count value of each of the plurality of data transfer circuits becomes above or below a predetermined set value.
In addition, the memory control circuit may be constructed as follows. In any of the plurality of data transfer circuits which considers the memory as a transfer source and considers the buffer as a transfer destination, if all the data stored in the buffer as the transfer destination is deleted in compliance with an external signal, number of pieces of data to be transferred one time by the data transfer circuit through a predetermined duration is made smaller than number of pieces of data to be transferred through a duration other than the predetermined duration, or the number of times the acknowledge signal is transmitted by said bus arbiter in response to the request signal transmitted by said data transfer circuit is made smaller through a predetermined duration than the number of times the acknowledge signal is transmitted by said bus arbiter in response to the request signal transmitted by said data transfer circuit through the duration other than the predetermined duration.
According to another aspect of the present invention, a method for arbitrating a memory bus includes the steps of (1) transmitting a request signal demanding start of the data transfer from each of the plurality of data transfer circuits to the bus arbiter on the basis of at least one of the count values of the plurality of counters, and (2) transmitting an acknowledge signal granting start of the data transfer from the bus arbiter to the data transfer circuit associated with the current state of the state machine, if the data transfer circuit associated with the current state of the state machine transmits the request signal to the bus arbiter. The method further includes the steps of (3) starting the data transfer of each of the plurality of data transfer circuits at receipt of the acknowledge signal from the bus arbiter in response to the request signal, and stopping the data transfer being executed on the basis of either number of pieces of data transferred after the receipt of the acknowledge signal or the count value of at least one of the plurality of counters, (4) not transmitting the acknowledge signal to the data transfer circuit associated with the current state of the state machine, when the data transfer circuit associated with the current state of the state machine either does not transmit the request signal or has stopped the data transfer being executed, transition of the current state of the state machine to a renewed current state taking place in accordance with the predetermined transition condition, and (5) repeating the steps (1) to (4).
According to yet another aspect of the present invention, a method for arbitrating a memory bus includes the steps of (1) transmitting a request signal demanding start of the data transfer from each of the plurality of data transfer circuits to the bus arbiter on the basis of at least one of the count values of the plurality of counters, (2) entering a data transfer instruction, which is associated with at least one of the plurality of data transfer circuits that has transmitted the request signal, into a tail of the instruction queue, if the bus arbiter has received the request signal from at least one of the plurality of data transfer circuits, and (3) transmitting an acknowledge signal granting start of the data transfer from the bus arbiter to the data transfer circuit associated with a data transfer instruction held at a head of the instruction queue. The method further includes the steps of (4) starting the data transfer of each of the plurality of data transfer circuits at receipt of the acknowledge signal from the bus arbiter in response to the request signal, and stopping the data transfer being executed on the basis of either number of pieces of data transferred after the receipt of the acknowledge signal or the count value of at least one of the plurality of counters, (5) deleting the data transfer instruction associated with the data transfer circuit that has stopped the data transfer from the instruction queue, and shifting contents of the instruction queue in a latter stage by one stage toward the head of the instruction queue, when the data transfer circuit has stopped the data transfer, and (6) repeating the steps (1) to (5).
According to yet another aspect of the present invention, a method for arbitrating a memory bus includes the steps of (1) transmitting a request signal demanding start of the data transfer from each of the plurality of data transfer circuits to the bus arbiter on the basis of at least one of the count values of the plurality of counters, (2) transmitting an acknowledge signal granting start of the data transfer to the data transfer circuit associated with the current state of the state machine, when the data transfer circuit associated with the current state of the state machine transmits the request signal to the bus arbiter, and (3) starting the data transfer of each of the plurality of data transfer circuits at receipt of the acknowledge signal from the bus arbiter in response to the request signal, and stopping the data transfer being executed on the basis of either number of pieces of data transferred after the receipt of the acknowledge signal or the count value of at least one of the plurality of counters. The method further includes the steps of (4) not transmitting the acknowledge signal to the data transfer circuit associated with the current state of the state machine, when the data transfer circuit associated with the current state of the state machine either does not transmit the request signal or has stopped the data transfer being executed, transition of the current state of the state machine to a renewed current state taking place in accordance with the predetermined transition condition, (5) executing at least a part of the data transfer instructions held in the instruction queue sequentially from the head of the instruction queue, only when the current state of the state machine is associated with the instruction queue, after that transition of the current state of the state machine to a renewed current state taking place in accordance with the predetermined transition condition, and (6) repeating the steps (1) to (5).